Resistive random-access memory (RRAM or ReRAM) is a non-volatile memory in which a dielectric that is normally insulating, is configured to conduct after application of a sufficiently high voltage. The forming of a conduction path typically requires a relatively high voltage. Once the path (e.g., filament) is formed in the dielectric, the path may be RESET (broken, to provide high resistance) or SET (re-formed, to provide a low resistance) by an appropriately applied voltage. As used herein, an operation where a RRAM cell, in a High-Resistive-State (HRS) changes to a Low-Resistive-State (LRS) is a SFT operation. Conversely, an operation where a RRAM cell in an LRS changes to an HRS is a RESET operation.
There are several approaches in creating a memory device from an RRAM element. To achieve a smallest bit-cell size, a cross-point cell configuration can be used, where a single memory element is used as a memory cell without a select transistor. Although small in dimension, such architecture is subject to “sneak” parasitic currents flowing through non-selected neighboring memory cells.
In order to suppress the “sneak” parasitic currents, complementary resistive switches may be used. Complementary resistive switches may include two RRAM cells of opposite polarity connected to each other in series. For example, for any SET or RESET direction, one cell is in an HRS while the other is in an LRS. In this regard, the total resistance of the two complementary cells, connected in series is Rtotal=RHRS+RLRS no matter which direction the cells are programmed. The advantage of a complementary switch configuration is the suppression of sneak path currents without the need for select devices (e.g., pass transistors). However, such configuration has the drawback of being subject to destructive read. Thus, every time the information of a memory cell is read, the memory content is destroyed. The memory content is typically recreated with an additional SET/RESET operation (e.g., write cycle).
Rewriting the content of the cell after every read reduces the life of a memory cell because the number of write operations is typically limited (e.g., 100,000 cycles). Additionally, recreating the information lost in the memory cell lowers the performance (i.e., speed), as a SET/RESET operation is required after every read access.
Another solution proposed to suppress the “sneak” parasitic currents is based on including a select transistor. For example, a one-transistor-one-resistor (1T1R) architecture has a select transistor to turn ON/OFF the path to the resistive cell. The drawback of the 1T1R RRAM configuration is that currents and/or voltages used for forming, SET, and RESET operations are passed through the select device. Using a select device poses a scaling challenge because RRAM cells generally require increasing forming voltages for decreasing bit-cell area. Further, SET/RESET conditions do not scale with bit-cell area. Thus, as the size of the RRAM is reduced, more current is required to flow through the pass transistor to perform a forming, SET, or RESET operation. However, as the RRAM cell in the 1T1R configuration is reduced, the select transistor cannot be reduced linearly with the resistive elements because it would not be able to accommodate the current requirements to perform the above operations. Accordingly, a 1T1R cell configuration poses a limitation for RRAM scaling.